Scott C. Smith
Professor and Department Chair
Also affiliated: University of Massachusetts Dartmouth (2000–2002); University of Central Florida (2001); North Carolina State University (1993); Texas A&M University – Kingsville (2019–2024); Missouri University of Science and Technology (2002–2025); Heriot-Watt University (2007); University of Minnesota Rochester (2003–2025); Maxim Integrated (United States) (2012); UK Astronomy Technology Centre (2007); North Dakota State University (2013–2019); University of Missouri (2020); Texas A&M University (2020–2023); Colorado State University (2020); University of Edinburgh (2007)
Research Areas
Biomedical Subjects
Links
Biography and Research Information
OverviewAI-generated summary
Scott C. Smith's research interests include cybersecurity, hardware security, and asynchronous circuit design. He has published work on security threat modeling for power transformers and photovoltaic systems, as well as ransomware security threat modeling for photovoltaic systems. His publications also address approximate memory for low-power video applications and FPGA acceleration of real-time neural network controllers for solar inverters.
Smith has also investigated illegal Trojan design and detection in asynchronous logic circuits, including NULL Convention Logic and Sleep Convention Logic. His work in this area includes built-in self-test for multi-threshold NULL Convention Logic asynchronous circuits using pipeline stage parallelism and combining relaxation with NCL_X for enhanced optimization of asynchronous Null Convention Logic circuits. He holds an h-index of 23, with 1,881 total citations across 127 publications. His recent collaborators include Kenneth Mordi and Jia Di, both from the University of Arkansas at Fayetteville.
Metrics
- h-index: 23
- Publications: 123
- Citations: 1,854
Positions
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Professor and Department Chair 2019–presentTexas A&M University Kingsville EECS ORCID
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Professor and Department Chair publications 2007–2025University of Arkansas at Fayetteville ORCID
Selected Publications
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Demonstration of the Benefits of Asynchronous vs. Synchronous Circuits (2025)
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Design of a Motor Control Board for the NASA Lunabotics Mining Competition (2025)
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Integrating Asynchronous Paradigms into a VLSI Design Course (2025)
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Integrating Asynchronous Digital Design And Testing Into The Undergraduate Computer Engineering Curriculum (2020)
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A robust, wide-temperature data transmission system for space environments (2013)
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Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design (2013)
Collaboration Network
Top Collaborators
- Designing Asynchronous Circuits using NULL Convention Logic (NCL)
- Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic
- Ultra-low power delay-insensitive circuit design
- Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology
- Side-channel attack mitigation using dual-spacer Dual-rail Delay-insensitive Logic (D3L)
Showing 5 of 14 shared publications
- Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
- Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL
- Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum
- Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Semi-Static NCL Circuits
- Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design
Showing 5 of 6 shared publications
- CMOS implementation comparison of NCL gates
- CMOS implementation of static threshold gates with hysteresis: A new approach
- Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
- CMOS Implementation of Threshold Gates with Hysteresis
- Designing Asynchronous Circuits using NULL Convention Logic (NCL)
- Delay-insensitive asynchronous ALU for cryogenic temperature environments
- Sequential NCL Circuit Design
- Comprehensive NCL Design Example
- Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic
- Side-channel attack mitigation using dual-spacer Dual-rail Delay-insensitive Logic (D3L)
- MTD 3 L: a secure IC design methodology with reduced overhead
- Ultra-low power delay-insensitive circuit design
- Delay-insensitive asynchronous ALU for cryogenic temperature environments
- A robust, wide-temperature data transmission system for space environments
- Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology
- Static implementation of quasi-delay-insensitive Pre-Charge Half-Buffers
- Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic
- Side-channel attack mitigation using dual-spacer Dual-rail Delay-insensitive Logic (D3L)
- Delay-insensitive asynchronous ALU for cryogenic temperature environments
- Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs
- Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL
- Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Semi-Static NCL Circuits
- Delay-Insensitive Cell Matrix.
- A differential design for C-elements and NCL gates
- Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic
- Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic
- Sleep Convention Logic using partially slept function blocks
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