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Confirmed
Presence
Current · Arkansas
Last published
2026
Sources
OpenAlex · ORCID
Refreshed
2026-10-05
L
Leonard W. Schaper
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
professor of electrical engineering at the University
Also affiliated: AT&T (United States) (1984); Alcoa (United States) (1992)
18 h-index
92 pubs
927 cited
Research Areas
Links
Biography and Research Information
OverviewAI-generated summary
Leonard W. Schaper's research focuses on the development and integration of processes for advanced semiconductor packaging, particularly emphasizing through-silicon vias (TSVs). His work has investigated the architectural implications and process development for 3-D very-large-scale integration (VLSI) using Z-axis interconnects. Schaper has studied the reliability of copper-filled TSVs and explored methods for controlling sidewall slope in silicon vias using plasma etching techniques. His publications also include work on nanoscale TSVs for IC stacking and the effects of process parameters on via formation in silicon via deep reactive ion etching. He has also conducted preliminary investigations into the machining behavior of diamond-coated cutting tools, relating post-deposition polishing of diamond films to this behavior. Schaper holds a Ph.D. and has a publication record of 93 papers, with an h-index of 18 and over 900 citations.
Metrics
- h-index: 18
- Publications: 92
- Citations: 927
Positions
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professor of electrical engineering at the University publications 1992–2026University of Arkansas at Fayetteville Listing
Selected Publications
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Alternative Processing Methods for Copper Through Silicon Vias (2026)
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New Niobium Pentoxide (Nb2O5) Integrated Capacitors for Decoupling Applications (2026)
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3-D VLSI Structure for High Power and High Speed Computation (2026)
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Integration of Tantalum Pentoxide Capacitors With Through-Silicon Vias (2011)
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Reliability study of through-silicon via (TSV) copper filled interconnects (2009)
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Integrated Capacitors with Nb2O5 Dielectric for Decoupling Applications (2009)
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3D-SiP: The latest miniaturization technology (2008)
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Integrated system development for 3-D VLSI (2008)
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Fabrication and testing of through-silicon vias used in three-dimensional integration (2008)
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Interconnect Process at the University of Arkansas (2008)
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Dual Process Dielectric Formation for Decoupling Capacitors on Flexible Substrates (2007)
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Effect of process parameters on via formation in Si using deep reactive ion etching (2007)
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Integrated System Development for 3-D VLSI (2007)
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High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors (2007)
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Effect of via profile on copper seed layer deposition for electroplating (2007)
Collaboration Network
Top Collaborators
S. L. Burkett
University of Alabama (US)
21 shared publications
- Process integration for through-silicon vias
- Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias
- Reliability study of through-silicon via (TSV) copper filled interconnects
- Control of sidewall slope in silicon vias using SF6∕O2 plasma etching in a conventional reactive ion etching tool
- Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development
Showing 5 of 21 shared publications
Simon S. Ang
20 shared publications
In database
- Reliability of flexible thin-film embedded resistors and electrical characterization of thin-film embedded capacitors and inductors
- Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects
- Electrical characterization of the interconnected mesh power system (IMPS) MCM topology
- A study of the high frequency performance of thin film capacitors for electronic packaging
- Y1Ba2Cu3O7–xmultilayer structures with a thick SiO2interlayer for multichip modules
Showing 5 of 20 shared publications
W.D. Brown
University of Arkansas at Fayetteville (US)
17 shared publications
- A preliminary investigation of the effect of post-deposition polishing of diamond films on the machining behavior of diamond-coated cutting tools
- Reliability of flexible thin-film embedded resistors and electrical characterization of thin-film embedded capacitors and inductors
- Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects
- A study of the high frequency performance of thin film capacitors for electronic packaging
- Artifacts in SPM measurements of thin films and coatings
Showing 5 of 17 shared publications
Richard K. Ulrich
University of Arkansas at Fayetteville (US)
12 shared publications
- Advanced decoupling in high performance IC packaging
- Dual process dielectric formation for decoupling capacitors on flexible substrates
- Dual Process Dielectric Formation for Decoupling Capacitors on Flexible Substrates
- Sputter-deposited yttrium–barium–copper–oxide multilayer structures incorporating a thick interlayer dielectric material
- Uniform copper electroplating for application to multichip modules
Showing 5 of 12 shared publications
S. Spiesshoefer
University of Arkansas at Fayetteville (US)
8 shared publications
- Process integration for through-silicon vias
- Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias
- Control of sidewall slope in silicon vias using SF6∕O2 plasma etching in a conventional reactive ion etching tool
- Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development
- IC stacking technology using fine pitch, nanoscale through silicon vias
Showing 5 of 8 shared publications
I. U. Abhulimen
Intel (United Kingdom) (GB)
8 shared publications
- Effect of process parameters on via formation in Si using deep reactive ion etching
- Fabrication and testing of through-silicon vias used in three-dimensional integration
- Back side exposure of variable size through silicon vias
- Effect of via profile on copper seed layer deposition for electroplating
- Integrated System Development for 3-D VLSI
Showing 5 of 8 shared publications
Hameed A. Naseem
University of Arkansas at Fayetteville
7 shared publications
In database
- A preliminary investigation of the effect of post-deposition polishing of diamond films on the machining behavior of diamond-coated cutting tools
- Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects
- A study of the high frequency performance of thin film capacitors for electronic packaging
- Thin film decoupling capacitors: a high frequency performance analysis
- CVD-diamond substrates for multi-chip modules (MCMs)
Showing 5 of 7 shared publications
S. Afonso
Honeywell (United States) (US)
7 shared publications
- Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects
- Fabrication of biaxially aligned YBa2Cu3O7−x thin films on glass substrates
- Y1Ba2Cu3O7–xmultilayer structures with a thick SiO2interlayer for multichip modules
- Magnetic field and temperature dependence of critical current densities in multilayer YBa2Cu3O7−δ films
- Signal propagation on seamless high off-chip connectivity (SHOCC) interconnects
Showing 5 of 7 shared publications
Li Cai
University of Arkansas at Fayetteville (US)
7 shared publications
- Effect of process parameters on via formation in Si using deep reactive ion etching
- Copper electroplating to fill blind vias for three-dimensional integration
- Back side exposure of variable size through silicon vias
- Effect of via profile on copper seed layer deposition for electroplating
- Integrated System Development for 3-D VLSI
Showing 5 of 7 shared publications
Y.L. Low
6 shared publications
- Electrical characterization of the interconnected mesh power system (IMPS) MCM topology
- Modeling and experimental verification of the interconnected mesh power system (IMPS) MCM topology
- Design of the Interconnected Mesh Power System (IMPS) MCM Topology
- A low-cost MCM design topology-the interconnected mesh power system (IMPS)
- The interconnected mesh power system (IMPS) MCM topology
Showing 5 of 6 shared publications
Greg Salamo
University of Arkansas at Fayetteville
6 shared publications
In database
- Fabrication of biaxially aligned YBa2Cu3O7−x thin films on glass substrates
- Y1Ba2Cu3O7–xmultilayer structures with a thick SiO2interlayer for multichip modules
- Magnetic field and temperature dependence of critical current densities in multilayer YBa2Cu3O7−δ films
- Sputter-deposited yttrium–barium–copper–oxide multilayer structures incorporating a thick interlayer dielectric material
- Curriculum restructure to answer critical needs in packaging for energy efficiency/renewable energy systems, wireless, and mixed-signal systems areas
Showing 5 of 6 shared publications
R. Ulrich
University of Arkansas at Fayetteville (US)
5 shared publications
- The "Stealth" decoupling capacitor
- Anodization for forming thin film embedded capacitors in MCM-D and MCM-L substrates
- High capacitance density thin film integrated tantalum pentoxide decoupling capacitors
- Curriculum restructure to answer critical needs in packaging for energy efficiency/renewable energy systems, wireless, and mixed-signal systems areas
- Novel, high density R/C terminating networks
J.P. Parkerson
University of Arkansas at Fayetteville
5 shared publications
In database
- Reliability of flexible thin-film embedded resistors and electrical characterization of thin-film embedded capacitors and inductors
- Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects
- Design considerations for using integrated passive components
- Signal propagation on seamless high off-chip connectivity (SHOCC) interconnects
- Advanced interconnected mesh power system (IMPS) MCM topologies
F. T. Chan
University of Arkansas at Fayetteville (US)
5 shared publications
- Fabrication of biaxially aligned YBa2Cu3O7−x thin films on glass substrates
- Y1Ba2Cu3O7–xmultilayer structures with a thick SiO2interlayer for multichip modules
- Magnetic field and temperature dependence of critical current densities in multilayer YBa2Cu3O7−δ films
- Fabrication and characterization of vias for contacting YBa2Cu3O7−x multilayers
- Fabrication techniques and electrical properties of YBa2Cu3O7−x multilayers with rf sputtered amorphous SiO2 interlayers
S. Polamreddy
University of Arkansas at Fayetteville (US)
5 shared publications
- Process integration for through-silicon vias
- Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias
- Effect of process parameters on via formation in Si using deep reactive ion etching
- Copper electroplating to fill blind vias for three-dimensional integration
- The Design of a Polishing Procedure for Investigating Profiles Formed by DRIE to Fabricate Through-Silicon Vias
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