David Andrews
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Assistant Professor
Also affiliated: Illinois College (2012); Anglian Water Services (United Kingdom) (1994); University of Dallas (2012–2023); European Commission (2012); Técnicas Reunidas (Spain) (1996); Joint Research Centre (2012); Braintree Community Hospital (2006); Directorate-General Joint Research Centre (2012); Joint Research Centre (2014); Transnational Press London (2020); Harbor Branch Oceanographic Institute (1984); Rice University (1999)
Faculty Researcher
Research Areas
Biomedical Subjects
Links
Biography and Research Information
OverviewAI-generated summary
David Andrews' research focuses on the intersection of computer engineering, machine learning, and cybersecurity. He has published work on hardware implementations of cryptographic algorithms, including a masked pure-hardware implementation of the Kyber cryptographic algorithm and power-based side-channel attack analysis on post-quantum cryptography algorithms. His work also extends to machine learning applications, with publications on high-rate machine learning for forecasting time-series signals and accelerating LSTM-based high-rate dynamic system models. Andrews has also investigated the development of specialized hardware for machine learning, such as a customizable domain-specific memory-centric FPGA overlay.
His research group at the University of Arkansas at Fayetteville collaborates with faculty members such as Miaoqing Huang, Ehsan Kabir, and Tendayi Kamucheka. Andrews has received funding for his work, including a $100,000 NSF grant as Co-PI for research on infrastructure to perform side-channel attacks on cryptographic algorithms. His scholarship metrics include an h-index of 10, with 33 total publications and 388 total citations.
Metrics
- h-index: 10
- Publications: 33
- Citations: 390
Selected Publications
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DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing (2025)
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N-TORC: Native Tensor Optimizer for Real-Time Constraints (2025)
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Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms (2025)
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Resource Scheduling for Real-Time Machine Learning (2025)
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Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs (2024)
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ProTEA: Programmable Transformer Encoder Acceleration on FPGA (2024)
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IMAGine: An In-Memory Accelerated GEMV Engine Overlay (2024)
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The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators (2024)
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Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators (2024)
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Towards Cloud-based Infrastructure for Post-Quantum Cryptography Side-channel Attack Analysis (2023)
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FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? (2023)
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Accelerating LSTM-Based High-Rate Dynamic System Models (2023)
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FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? (2023)
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Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays (2023)
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A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA (2022)
Federal Grants 1 $100,000 total
Collaboration Network
Top Collaborators
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA
Showing 5 of 16 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- ProTEA: Programmable Transformer Encoder Acceleration on FPGA
Showing 5 of 13 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA
- ProTEA: Programmable Transformer Encoder Acceleration on FPGA
Showing 5 of 8 shared publications
- An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks
- High-Rate Machine Learning for Forecasting Time-Series Signals
- A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
Showing 5 of 6 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Resource Scheduling for Real-Time Machine Learning
- Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms
Showing 5 of 6 shared publications
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
Showing 5 of 6 shared publications
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
- Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks
- Towards Cloud-based Infrastructure for Post-Quantum Cryptography Side-channel Attack Analysis
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
- A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- Resource Scheduling for Real-Time Machine Learning
- N-TORC: Native Tensor Optimizer for Real-Time Constraints
- Resource Scheduling for Real-Time Machine Learning
- N-TORC: Native Tensor Optimizer for Real-Time Constraints
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