Match tier
Listed
Presence
Current · Arkansas
Last published
2025
Sources
OpenAlex · ORCID
Refreshed
2026-08-08
M
MD Arafat Kabir
Researcher
Also affiliated: Seva Mandir (2025); Seattle University (2025)
Unknown Researcher
2 h-index
5 pubs
17 cited
Research Areas
Links
Biography and Research Information
OverviewAI-generated summary
MD Arafat Kabir's research focuses on the co-optimization of chiplet and package designs for advanced computing systems. His work investigates methods for integrating components such as Field-Programmable Gate Arrays (FPGAs) and in-memory computing architectures to enhance performance and efficiency. Kabir has published on topics including holistic chiplet-package co-optimization for 2.5-D designs, flexible accelerators for transformer attention mechanisms on FPGAs, and in-memory accelerated engines.
His publications also explore cross-boundary inductive timing optimization and holistic in-context design flows for chiplet-package interactions. Kabir collaborates with researchers at the University of Arkansas at Fayetteville, including David Andrews and Miaoqing Huang, with whom he shares multiple publications. His h-index is 2, with a total of 5 publications and 17 citations.
Metrics
- h-index: 2
- Publications: 5
- Citations: 17
Selected Publications
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DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing (2025)
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Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs (2024)
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IMAGine: An In-Memory Accelerated GEMV Engine Overlay (2024)
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The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators (2024)
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FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? (2023)
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FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? (2023)
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Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays (2023)
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A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization (2021)
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Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design (2021)
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Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization (2021)
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Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design (2021)
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Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study (2020)
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Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design (2020)
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Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools (2020)
Collaboration Network
Top Collaborators
Jason D. Bakos
University of South Carolina (US)
7 shared publications
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
Showing 5 of 7 shared publications
Miaoqing Huang
University of Arkansas at Fayetteville
7 shared publications
In database
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
Showing 5 of 7 shared publications
David Andrews
University of Arkansas at Fayetteville
7 shared publications
In database
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
Showing 5 of 7 shared publications
Yarui Peng
University of Arkansas at Fayetteville
4 shared publications
In database
- Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design
- Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
- A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization
Joshua Hollis
University of Arkansas at Fayetteville
3 shared publications
In database
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Atiyehsadat Panahi
University of South Carolina (US)
3 shared publications
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Ehsan Kabir
University of Arkansas at Fayetteville
3 shared publications
In database
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Tendayi Kamucheka
University of Arkansas at Fayetteville
3 shared publications
In database
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
Nathaniel Fredricks
University of Arkansas at Fayetteville
3 shared publications
In database
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
Dusan Petranovic
Siemens (Hungary) (HU)
2 shared publications
- Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
- A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization
Eli Levy-Mackay
University of Arkansas at Fayetteville
2 shared publications
In database
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Joel Mandebi
Advanced Micro Devices (Canada) (CA)
2 shared publications
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
Weishiun Hung
National Tsing Hua University (TW)
1 shared publication
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
Tsung-Yi Ho
National Tsing Hua University (TW)
1 shared publication
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
Austin Downey
University of South Carolina (US)
1 shared publication
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
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