Miaoqing Huang
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Associate Professor
Also affiliated: George Washington University (2006–2010); University of Arkansas System (2024); Catholic University of America (2011)
Research Areas
Biomedical Subjects
Links
Biography and Research Information
OverviewAI-generated summary
Miaoqing Huang is an Associate Professor at the University of Arkansas at Fayetteville. His research interests lie in high-performance computing, particularly reconfigurable computing, and hardware architectures for cryptographic algorithms. Huang has published work on topics such as hardware implementations of post-quantum cryptography, optimizing Montgomery modular multiplication algorithms, and exploiting concurrency on graphic processing units.
His research has been supported by funding from the National Science Foundation (NSF) for a project focused on infrastructure for side-channel attacks on cryptographic algorithms, totaling $100,000. Huang has a significant publication record, with 113 total publications and an h-index of 15, accumulating over 1,000 citations. He actively collaborates with researchers at the University of Arkansas, including David Andrews, Ehsan Kabir, MD Arafat Kabir, and Tendayi Kamucheka, with whom he has co-authored numerous publications.
Metrics
- h-index: 15
- Publications: 108
- Citations: 1,056
Positions
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Associate Professor 2023–presentUniversity of Arkansas Department of Electrical Engineering and Computer Science ORCID
Selected Publications
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Extreme precipitation (2025)
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A runtime-adaptive transformer neural network accelerator on FPGAs (2025)
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DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing (2025)
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Enhancing Efficiency in Statistical Modeling of Wildfire Aerosols: A Heterogeneous Approach with R and GPU Acceleration (2025)
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N-TORC: Native Tensor Optimizer for Real-Time Constraints (2025)
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Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms (2025)
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Resource Scheduling for Real-Time Machine Learning (2025)
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Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs (2024)
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ProTEA: Programmable Transformer Encoder Acceleration on FPGA (2024)
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IMAGine: An In-Memory Accelerated GEMV Engine Overlay (2024)
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The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators (2024)
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A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs (2024)
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An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain–computer interfaces (2024)
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Towards Cloud-based Infrastructure for Post-Quantum Cryptography Side-channel Attack Analysis (2023)
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FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? (2023)
Federal Grants 1 $100,000 total
Collaboration Network
Top Collaborators
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- Modular Design of Fully Pipelined Reduction Circuits on FPGAs
- Scalable Memory Hierarchies for Embedded Manycore Systems
- Developing application-specific multiprocessor platforms on FPGAs
- High-Rate Machine Learning for Forecasting Time-Series Signals
Showing 5 of 22 shared publications
- A hybrid parallel cellular automata model for urban growth simulation over GPU/CPU heterogeneous architectures
- Geocomputation over the Emerging Heterogeneous Computing Infrastructure
- Unsupervised image classification over supercomputers Kraken, Keeneland and Beacon
- Accelerating Geospatial Applications on Hybrid Architectures
- Comparison of Parallel Programming Models on Intel MIC Computer Cluster
Showing 5 of 16 shared publications
- A hybrid parallel cellular automata model for urban growth simulation over GPU/CPU heterogeneous architectures
- Geocomputation over the Emerging Heterogeneous Computing Infrastructure
- Accelerating Mean Shift Segmentation Algorithm on Hybrid CPU/GPU Platforms
- Unsupervised image classification over supercomputers Kraken, Keeneland and Beacon
- Accelerating Geospatial Applications on Hybrid Architectures
Showing 5 of 15 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- ProTEA: Programmable Transformer Encoder Acceleration on FPGA
Showing 5 of 14 shared publications
- A unified OpenCL-flavor programming model with scalable hybrid hardware platform on FPGAs
- Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures
- Improve memory access for achieving both performance and energy efficiencies on heterogeneous systems
- OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-Oriented Programming Methods
- PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system
Showing 5 of 10 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Showing 5 of 9 shared publications
- Exploiting concurrent kernel execution on graphic processing units
- Scaling scientific applications on clusters of hybrid multicore/GPU nodes
- Efficient cache design for solid-state drives
- Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants
- Towards efficient GPU sharing on multicore processors
Showing 5 of 6 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Resource Scheduling for Real-Time Machine Learning
- Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms
Showing 5 of 6 shared publications
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
Showing 5 of 6 shared publications
- Geocomputation over the Emerging Heterogeneous Computing Infrastructure
- Unsupervised image classification over supercomputers Kraken, Keeneland and Beacon
- Accelerating Geospatial Applications on Hybrid Architectures
- Comparison of Parallel Programming Models on Intel MIC Computer Cluster
- Study of parallel programming models on computer clusters with Intel MIC coprocessors
- Scalable Memory Hierarchies for Embedded Manycore Systems
- Developing application-specific multiprocessor platforms on FPGAs
- Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures
- OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-Oriented Programming Methods
- A Hierarchical Memory Architecture with NoC Support for MPSoC on FPGAs
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
- Benchmark of Acceleware vs XFdtd for Field Simulations of Microstrip Patch Antenna
- Exploiting concurrent kernel execution on graphic processing units
- Scaling scientific applications on clusters of hybrid multicore/GPU nodes
- Towards efficient GPU sharing on multicore processors
- Towards efficient GPU sharing on multicore processors
- High-Rate Machine Learning for Forecasting Time-Series Signals
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Scaling scientific applications on clusters of hybrid multicore/GPU nodes
- Efficient cache design for solid-state drives
- Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants
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