Miaoqing Huang
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Associate Professor
Faculty Researcher
Research Areas
Biomedical Subjects
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Biography and Research Information
OverviewAI-generated summary
Miaoqing Huang, an Associate Professor at the University of Arkansas at Fayetteville, leads a research group focused on advanced computing and its applications. Huang's work encompasses areas such as cryptographic algorithms, machine learning for time-series forecasting, and neural network applications for signal processing. Huang has received federal funding from the National Science Foundation (NSF) for a project focused on infrastructure to perform side-channel attacks on cryptographic algorithms, receiving $100,000 as Principal Investigator (PI). This work involves collaboration with colleagues at the University of Arkansas at Fayetteville, including David Andrews and Ehsan Kabir.
Huang's recent publications demonstrate a breadth of research interests. These include hardware implementations of cryptographic algorithms like Kyber, self-supervised domain adaptation for crowd counting, and power-based side-channel attack analysis on post-quantum cryptography. Further research extends to optimized EEGNet processors for wearable brain-computer interfaces, high-rate machine learning for time-series forecasting, and accelerating LSTM-based dynamic system models. Additionally, Huang has investigated end-to-end graph neural networks for fMRI datasets and explored FPGA processor-in-memory architectures.
With a h-index of 15 and over 1,000 citations across 113 publications, Huang has established a significant research presence. The researcher's recent activity and ongoing lab website indicate a continued commitment to advancing computational methodologies and exploring their practical implications.
Metrics
- h-index: 15
- Publications: 113
- Citations: 1,030
Selected Publications
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Extreme precipitation (2025)
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A runtime-adaptive transformer neural network accelerator on FPGAs (2025)
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DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing (2025)
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Enhancing Efficiency in Statistical Modeling of Wildfire Aerosols: A Heterogeneous Approach with R and GPU Acceleration (2025)
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N-TORC: Native Tensor Optimizer for Real-Time Constraints (2025)
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Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms (2025)
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Resource Scheduling for Real-Time Machine Learning (2025)
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Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs (2024)
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ProTEA: Programmable Transformer Encoder Acceleration on FPGA (2024)
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IMAGine: An In-Memory Accelerated GEMV Engine Overlay (2024)
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The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators (2024)
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A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs (2024)
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An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain–computer interfaces (2024)
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Towards Cloud-based Infrastructure for Post-Quantum Cryptography Side-channel Attack Analysis (2023)
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FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? (2023)
Federal Grants 1 $100,000 total
Collaboration Network
Top Collaborators
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA
Showing 5 of 14 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- ProTEA: Programmable Transformer Encoder Acceleration on FPGA
Showing 5 of 13 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA
- ProTEA: Programmable Transformer Encoder Acceleration on FPGA
Showing 5 of 8 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- Accelerating LSTM-Based High-Rate Dynamic System Models
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Resource Scheduling for Real-Time Machine Learning
- Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms
Showing 5 of 6 shared publications
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
Showing 5 of 6 shared publications
- High-Rate Machine Learning for Forecasting Time-Series Signals
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing
- A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
- Towards Cloud-based Infrastructure for Post-Quantum Cryptography Side-channel Attack Analysis
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
- An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain–computer interfaces
- A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs
- An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain–computer interfaces
- A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs
- IMAGine: An In-Memory Accelerated GEMV Engine Overlay
- The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
- ProTEA: Programmable Transformer Encoder Acceleration on FPGA
- Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms
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