Hui Wang Data-verified
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Biography and Research Information
OverviewAI-generated summary
Hui Wang's research program centers on semiconductor materials and devices, with a particular focus on silicon carbide (SiC) technology. Wang has investigated the characterization of SiC Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), including their gate-oxide degradation under various stress conditions and performance at high temperatures. The research also extends to the design and fabrication of SiC devices for specific applications, such as electrostatic discharge (ESD) protection. Additionally, Wang's work encompasses other semiconductor technologies, including dual-bit/cell split-gate floating-gate flash memory cells. Recent publications also indicate an interest in metasurfaces for terahertz beam manipulation. Wang collaborates with several researchers at the University of Arkansas at Fayetteville, including Pengyu Lai and Zhong Chen, with whom they have multiple shared publications. Wang has published 82 papers, accumulating 978 citations and an h-index of 15.
Metrics
- h-index: 15
- Publications: 82
- Citations: 1,002
Selected Publications
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Fabrication and Characterization of 4H-SiC Schottky Barrier Diodes with Highly Linear Temperature Sensitivity (2025)
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TCAD-Aided Investigation of Temperature-Dependent Behavior in 4H-SiC P-Channel MOSFETs Up to 500°C (2025)
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<i>(Invited)</i> High-Temperature Reliability of Ti-Based Ohmic Contacts to SiC (2025)
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Design Optimizations of Micrometer SiC CMOS Devices for High-Temperature IC Applications (2025)
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Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures (2024)
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Electrical Safe Operating Area and Latent Damage of SiC Low-Voltage nMOS Under TLP and VF-TLP Stresses (2024)
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A review of silicon carbide CMOS technology for harsh environments (2024)
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Current Injection Effect on ESD Behaviors of the Parasitic Bipolar Transistors inside P+/N-well diode (2023)
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Characterization of Gate-Oxide Degradation Location for SiC MOSFETs Based on the Split <i>C–V</i> Method Under Bias Temperature Instability Conditions (2023)
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Area-Efficient Silicon Carbide SCR Device for On-Chip ESD Protection (2022)
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Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections (2021)
Collaboration Network
Top Collaborators
- A review of silicon carbide CMOS technology for harsh environments
- Area-Efficient Silicon Carbide SCR Device for On-Chip ESD Protection
- Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures
- Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections
- Electrical Safe Operating Area and Latent Damage of SiC Low-Voltage nMOS Under TLP and VF-TLP Stresses
Showing 5 of 8 shared publications
- A review of silicon carbide CMOS technology for harsh environments
- Characterization of Gate-Oxide Degradation Location for SiC MOSFETs Based on the Split <i>C–V</i> Method Under Bias Temperature Instability Conditions
- Area-Efficient Silicon Carbide SCR Device for On-Chip ESD Protection
- Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures
- Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections
Showing 5 of 7 shared publications
- A review of silicon carbide CMOS technology for harsh environments
- Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures
- Electrical Safe Operating Area and Latent Damage of SiC Low-Voltage nMOS Under TLP and VF-TLP Stresses
- Design Optimizations of Micrometer SiC CMOS Devices for High-Temperature IC Applications
- <i>(Invited)</i> High-Temperature Reliability of Ti-Based Ohmic Contacts to SiC
- Day-ahead scheduling model for integrated energy system with demand response and responsible consumption weights
- Optimal dispatching of integrated energy system considering flexible load
- Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology
- The SAS Implant Integration Optimization in the Cell Scaling of 4Xnm ETOX NOR Flash
- Area-Efficient Silicon Carbide SCR Device for On-Chip ESD Protection
- Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures
- Current Injection Effect on ESD Behaviors of the Parasitic Bipolar Transistors inside P+/N-well diode
- <i>(Invited)</i> High-Temperature Reliability of Ti-Based Ohmic Contacts to SiC
- A review of silicon carbide CMOS technology for harsh environments
- <i>(Invited)</i> High-Temperature Reliability of Ti-Based Ohmic Contacts to SiC
- A review of silicon carbide CMOS technology for harsh environments
- Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures
- Design Optimizations of Micrometer SiC CMOS Devices for High-Temperature IC Applications
- <i>(Invited)</i> High-Temperature Reliability of Ti-Based Ohmic Contacts to SiC
- Modeling and application for rolling scheduling problem based on TSP
- Modeling and application for rolling scheduling problem based on TSP
- Modeling and application for rolling scheduling problem based on TSP
- Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections
- Area-efficient dual-diode with optimized parasitic bipolar structure for rail-based ESD protections
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