Yarui Peng
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Junior Chair Professor
Also affiliated: Georgia Institute of Technology (2013–2017); Taiwan Semiconductor Manufacturing Company (United States) (2010); Sun Yat-sen University (2022); Taiwan Semiconductor Manufacturing Company (Taiwan) (2010); Wuhan Union Hospital (2020); Sun Yat-sen University Cancer Center (2022); State Key Laboratory of Oncology in South China (2022); Huazhong University of Science and Technology (2020)
Faculty Researcher
Research Areas
Biomedical Subjects
Links
Biography and Research Information
OverviewAI-generated summary
Yarui Peng's research focuses on computer-aided design, analysis, and optimization for very-large-scale integration (VLSI) circuits and emerging technologies. His work investigates methodologies and algorithms for parasitic extraction, signal integrity analysis and optimization, and the mitigation of reliability issues in thermal and power delivery for 2.5D and 3D integrated circuits (ICs). Peng also studies the improvement of electro-thermal reliability in power systems, such as multi-chip power modules (MCPMs), through layout synthesis and simultaneous optimization of heat dissipation and electrical performance.
Peng received his B.S. from Tsinghua University and M.S. and Ph.D. degrees from Georgia Institute of Technology. He is currently an Assistant Professor in the Computer Science and Computer Engineering Department at the University of Arkansas. He also collaborates with the NSF-sponsored Engineering Research Center for Power Optimization of Electro-Thermal Systems. His work has been supported by the National Science Foundation (NSF) through a CAREER award totaling $500,000 for research on chiplet-package co-optimizations for 2.5D heterogeneous systems-on-chips (SoCs).
With a h-index of 14 and over 764 citations across 65 publications, Peng actively collaborates with researchers at the University of Arkansas, including Imam Al Razi, Quang Trung Le, Tristan M. Evans, and David Huitink. He maintains an active lab website to share his research activities.
Metrics
- h-index: 15
- Publications: 65
- Citations: 803
Selected Publications
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PowerSynth 2: Automated Power Electronics Physical Design Synthesis With Custom and Heterogeneous Components (2025)
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Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System (2025)
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Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth (2023)
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VLSI-Inspired Design Automation for Scalable Power Electronics Layout Optimization (2023)
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A Comparative Study on Optimization Algorithms in PowerSynth 2 (2023)
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Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules (2023)
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Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules (2023)
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PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules (2022)
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Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth (2022)
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Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization (2022)
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Design Challenges of Intrachiplet and Interchiplet Interconnection (2022)
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Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses (2022)
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Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation (2021)
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Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method (2021)
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A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization (2021)
Federal Grants 1 $500,000 total
CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs
Collaboration Network
Top Collaborators
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method
- PowerSynth-Guided Reliability Optimization of Multi-Chip Power Module
Showing 5 of 12 shared publications
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Placement and Routing for Power Module Layout
- Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method
Showing 5 of 12 shared publications
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method
- PowerSynth Integrated CAD flow for High Density Power Modules
Showing 5 of 7 shared publications
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Placement and Routing for Power Module Layout
- Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization
Showing 5 of 6 shared publications
- PowerSynth-Guided Reliability Optimization of Multi-Chip Power Module
- Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth
- Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design
- Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
- Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System
- Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth
- A Comparative Study on Optimization Algorithms in PowerSynth 2
- PowerSynth 2: Automated Power Electronics Physical Design Synthesis With Custom and Heterogeneous Components
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
- A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
- Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
- Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System
- Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
- A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
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