Research Areas
Biography and Research Information
OverviewAI-generated summary
John Venker's research focuses on the design and implementation of analog and mixed-signal integrated circuits, with a particular emphasis on low-power applications and advanced semiconductor technologies. His recent work includes the development of a low-power analog cell for spiking neural networks in 65 nm CMOS technology and a high-performance bandgap voltage reference for low-dropout voltage regulators in 22nm FD-SOI. Venker also investigates methods for extracting threshold voltage in silicon carbide MOSFETs at high temperatures, contributing to the understanding of materials for power electronics. His research collaborations include work with Abu Shahir Md Khalid Hasan, Jeff Dix, Md Maksudul Hossain, and Nicolaus Vail at the University of Arkansas at Fayetteville.
Metrics
- h-index: 2
- Publications: 3
- Citations: 10
Selected Publications
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A 0.8 V Bandgap Voltage Reference with High PSRR for Low-Dropout Voltage Regulator in 22nm FD-SOI (2024)
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Threshold Voltage Extraction Method for Low-Voltage SiC MOSFETs at High-Temperature (2023)
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A Low-Power Analog Cell for Implementing Spiking Neural Networks in 65 nm CMOS (2023)
Collaboration Network
Top Collaborators
- A Low-Power Analog Cell for Implementing Spiking Neural Networks in 65 nm CMOS
- A 0.8 V Bandgap Voltage Reference with High PSRR for Low-Dropout Voltage Regulator in 22nm FD-SOI
- A 0.8 V Bandgap Voltage Reference with High PSRR for Low-Dropout Voltage Regulator in 22nm FD-SOI
- Threshold Voltage Extraction Method for Low-Voltage SiC MOSFETs at High-Temperature
- A 0.8 V Bandgap Voltage Reference with High PSRR for Low-Dropout Voltage Regulator in 22nm FD-SOI
- Threshold Voltage Extraction Method for Low-Voltage SiC MOSFETs at High-Temperature
- A 0.8 V Bandgap Voltage Reference with High PSRR for Low-Dropout Voltage Regulator in 22nm FD-SOI
- Threshold Voltage Extraction Method for Low-Voltage SiC MOSFETs at High-Temperature
- A Low-Power Analog Cell for Implementing Spiking Neural Networks in 65 nm CMOS
- Threshold Voltage Extraction Method for Low-Voltage SiC MOSFETs at High-Temperature
- Threshold Voltage Extraction Method for Low-Voltage SiC MOSFETs at High-Temperature
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