Aireen Amir Jalal Data-verified
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Researcher
unknown
Research Areas
Biography and Research Information
OverviewAI-generated summary
Aireen Amir Jalal investigates advancements in semiconductor materials and devices, with a focus on integrated circuit design and harsh environment applications. Her work includes developing compact models for ferroelectric capacitors and MOSFETs, contributing to the design of materials like AlScN and β-Ga2O3 for integrated circuits. Jalal has also explored readout interfaces for Hall-effect sensors, relevant for both DC and high-frequency current measurements. Her research outputs include publications on open-source ASIC implementations of Chisel-generated System on a Chip designs. Jalal collaborates with researchers at the University of Arkansas at Fayetteville, including Abu Shahir Md Khalid Hasan and Md Majharul Islam, with whom she has co-authored multiple publications. Her academic contributions are reflected in a h-index of 3 and a total of 9 publications with 24 citations.
Metrics
- h-index: 3
- Publications: 9
- Citations: 24
Selected Publications
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Parametric Analysis of an AlScN Based Ferroelectric Capacitor Model in a Ferroelectric Memory Bitcell (2025)
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Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET (2025)
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Compact Model for a Ferroelectric Capacitor Compatible with Integrated Circuit Design in Harsh Environment (2025)
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Notch filter based Readout Interface for Hall-effect sensors for DC and High-Frequency Currents (2025)
Collaboration Network
Top Collaborators
- Compact Model for a Ferroelectric Capacitor Compatible with Integrated Circuit Design in Harsh Environment
- Notch filter based Readout Interface for Hall-effect sensors for DC and High-Frequency Currents
- Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- IBTIDA: Fully open-source ASIC implementation of Chisel-generated System on a Chip
- Compact Model for a Ferroelectric Capacitor Compatible with Integrated Circuit Design in Harsh Environment
- Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET
- Notch filter based Readout Interface for Hall-effect sensors for DC and High-Frequency Currents
- Notch filter based Readout Interface for Hall-effect sensors for DC and High-Frequency Currents
- Compact Model for a Ferroelectric Capacitor Compatible with Integrated Circuit Design in Harsh Environment
- Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET
- Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET
- Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET
- Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET
- Compact Modeling of <i>β</i> -Ga <sub>2</sub> O <sub>3</sub> Lateral Depletion Mode MOSFET
- Parametric Analysis of an AlScN Based Ferroelectric Capacitor Model in a Ferroelectric Memory Bitcell
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