Quang Trung Le
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Dean of Graduate School and Intern
Also affiliated: University of Kassel (2020); Goethe University Frankfurt (2018); Université Européenne de Bretagne (2010–2011); Centre National de la Recherche Scientifique (2007–2011); Asahi Kasei (Germany) (2020); Merck KGaA, Darmstadt (Germany) (2014–2015); Orange (France) (2011–2014); Technische Universität Darmstadt (2012–2018); FORCE Technology (Denmark) (2002); Optical Fiber Solutions (Denmark) (2004); Siemens (United States) (2021); Fonctions Optiques pour les Technologies de l’information (2007–2011); Université de Rennes (2007–2010)
Research Areas
Biomedical Subjects
Links
Biography and Research Information
OverviewAI-generated summary
Quang Trung Le's research focuses on the design automation of power modules and optical devices. He has developed tools such as PowerSynth for generating layouts of power modules, including hierarchical, heterogeneous, and high-density 3-D configurations. His work also extends to optical technologies, investigating devices like MEMS VCSELs for direct modulation and quantum-dash mode-locked lasers for high-speed data modulation in wavelength-division multiplexing applications. Le has explored remotely dual-pumped long-reach PONs and all-optical clock recovery systems utilizing quantum-dot lasers.
With 111 total publications and an h-index of 14, Le has collaborated with researchers including Yarui Peng and Imam Al Razi at the University of Arkansas at Fayetteville. His research has addressed the technology, assembly, and testing of W-band traveling wave tubes for 5G networks. Le's contributions span the fields of electrical engineering, computer science, and optical communications.
Metrics
- h-index: 14
- Publications: 111
- Citations: 744
Positions
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Dean of Graduate School and Intern publications 2016–2022University of Arkansas at Fayetteville Listing
Selected Publications
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PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules (2022)
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Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization (2022)
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Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses (2022)
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Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation (2021)
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Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method (2021)
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PowerSynth Integrated CAD flow for High Density Power Modules (2021)
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PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules (2021)
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Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization (2020)
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PowerSynth progression on layout optimization for reliability and signal integrity (2020)
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Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization (2019)
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Hierarchical Layout Synthesis and Design Automation for 2.5D Heterogeneous Multi-Chip Power Modules (2019)
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PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization (2019)
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Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Reliability Optimization (2018)
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Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts (2018)
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PowerSynth: A Power Module Layout Generation Tool (2018)
Collaboration Network
Top Collaborators
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization
Showing 5 of 16 shared publications
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
Showing 5 of 16 shared publications
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Reliability Optimization
Showing 5 of 11 shared publications
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
Showing 5 of 10 shared publications
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)
Showing 5 of 7 shared publications
- PowerSynth: A Power Module Layout Generation Tool
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)
- Fast transient thermal and power dissipation modeling for multi-chip power modules: A preliminary assessment of different electro-thermal evaluation methods
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization
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