Match tier
Confirmed
Presence
Formerly Arkansas
Last published
2026
Sources
OpenAlex · ORCID
Refreshed
2026-08-16
S
Shilpi Mukherjee
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Graduate Research Assistant
Formerly Arkansas Affiliated with University of Arkansas through 2023; recent publications list Cree (China).
Graduate Student Researcher
8 h-index
17 pubs
236 cited
Research Areas
Links
Biography and Research Information
OverviewAI-generated summary
Shilpi Mukherjee's research focuses on the design automation of multichip power modules, particularly investigating methods for improving efficiency and reliability. Her work includes developing automated design flows, such as PowerSynth, for hierarchical and heterogeneous 2.5-D power modules. Mukherjee has explored strategies to reduce partial discharge in high-voltage silicon carbide (SiC) power modules through specialized substrate designs and has investigated fast and accurate parasitic extraction techniques that account for eddy-current losses in multichip module designs. She also works on modeling approaches for partial discharge inception voltage and has studied the lifetime of SiC discrete MOSFETs under power cycling stress. Mukherjee collaborates with researchers H. Alan Mantooth, Tristan M. Evans, Quang Trung Le, and Yarui Peng at the University of Arkansas at Fayetteville.
Metrics
- h-index: 8
- Publications: 17
- Citations: 236
Selected Publications
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A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction (2023)
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A Partial Discharge Inception Voltage Modeling Approach (2023)
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Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses (2022)
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PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules (2021)
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General Equation to Determine Design Rules for Mitigating Partial Discharge and Electrical Breakdown in Power Module Layouts (2020)
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Electronic Design Automation (EDA) Tools and Considerations for Electro-Thermo-Mechanical Co-Design of High Voltage Power Modules (2020)
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Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts (2018)
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PowerSynth: A Power Module Layout Generation Tool (2018)
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Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs) (2017)
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Fast transient thermal and power dissipation modeling for multi-chip power modules: A preliminary assessment of different electro-thermal evaluation methods (2016)
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Energy Demand Analysis of Photovoltaic Device – Material and Nanomanufacturing Process Discovery (2015)
Collaboration Network
Top Collaborators
H. Alan Mantooth
University of Arkansas at Fayetteville
4 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- A Partial Discharge Inception Voltage Modeling Approach
Tristan M. Evans
University of Arkansas at Fayetteville
3 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- A Partial Discharge Inception Voltage Modeling Approach
Imam Al Razi
University of Arkansas at Fayetteville
2 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
Quang Trung Le
University of Arkansas at Fayetteville
2 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
Yarui Peng
University of Arkansas at Fayetteville
2 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
David Huitink
University of Arkansas at Fayetteville
1 shared publication
In database
- A Partial Discharge Inception Voltage Modeling Approach
Xiaoling Li
University of Arkansas at Fayetteville
1 shared publication
In database
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Hao Chen
University of Arkansas at Fayetteville (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Riya Paul
University of Arkansas at Fayetteville (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Xia Du
University of Arkansas at Fayetteville (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Robert Cuzner
University of Wisconsin–Milwaukee (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Xiaoqing Song
University of Arkansas at Fayetteville
1 shared publication
In database
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Yue Zhao
University of Arkansas at Fayetteville
1 shared publication
In database
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
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