S
Shilpi Mukherjee Data-verified
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Graduate Research Assistant
grad_student
8 h-index
17 pubs
236 cited
Research Areas
Links
Biography and Research Information
OverviewAI-generated summary
Shilpi Mukherjee's research focuses on the design automation of multichip power modules. Her work includes developing PowerSynth, a design automation flow for hierarchical and heterogeneous 2.5-D multichip power modules, as detailed in her 2021 publication. She has also investigated methods to reduce partial discharge in power modules, including a 10 kV SiC power module stack design published in 2023, and a modeling approach for partial discharge inception voltage. Additionally, Mukherjee has explored fast and accurate parasitic extraction in power module design, considering eddy-current losses, as presented in a 2022 publication. Her research is supported by collaborations with H. Alan Mantooth, Tristan M. Evans, Quang Trung Le, and Yarui Peng at the University of Arkansas at Fayetteville.
Metrics
- h-index: 8
- Publications: 17
- Citations: 236
Selected Publications
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A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction (2023)
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A Partial Discharge Inception Voltage Modeling Approach (2023)
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Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses (2022)
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PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules (2021)
Collaboration Network
Top Collaborators
H. Alan Mantooth
University of Arkansas at Fayetteville
4 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- A Partial Discharge Inception Voltage Modeling Approach
Tristan M. Evans
University of Arkansas at Fayetteville
3 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- A Partial Discharge Inception Voltage Modeling Approach
Imam Al Razi
University of Arkansas at Fayetteville
2 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
Quang Trung Le
University of Arkansas at Fayetteville
2 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
Yarui Peng
University of Arkansas at Fayetteville
2 shared publications
In database
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
David Huitink
University of Arkansas at Fayetteville
1 shared publication
In database
- A Partial Discharge Inception Voltage Modeling Approach
Xiaoling Li
University of Arkansas at Fayetteville (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Hao Chen
University of Arkansas at Fayetteville (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Riya Paul
University of Arkansas at Fayetteville (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Xia Du
University of Arkansas at Fayetteville (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Robert Cuzner
University of Wisconsin–Milwaukee (US)
1 shared publication
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Xiaoqing Song
University of Arkansas at Fayetteville
1 shared publication
In database
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
Yue Zhao
University of Arkansas at Fayetteville
1 shared publication
In database
- A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction
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