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Confirmed
Presence
Current · Arkansas
Last published
2025
Sources
OpenAlex · ORCID
Refreshed
2026-10-09
Y
Yarui Peng
Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.
Federal Grant PI
Junior Chair Professor
Also affiliated: Georgia Institute of Technology (2013–2017); Taiwan Semiconductor Manufacturing Company (United States) (2010); Taiwan Semiconductor Manufacturing Company (Taiwan) (2010); Sun Yat-sen University Cancer Center (2022); State Key Laboratory of Oncology in South China (2022)
15 h-index
63 pubs
806 cited
Research Areas
Biomedical Subjects
Links
Biography and Research Information
OverviewAI-generated summary
Yarui Peng's research focuses on computer-aided design, analysis, and optimization for very-large-scale integration (VLSI) circuits and emerging technologies. His work includes developing methodologies and algorithms for parasitic extraction, signal integrity analysis and optimization, and addressing reliability issues in thermal and power delivery for 2.5D and 3D integrated circuits (ICs). He also investigates methods to improve electro-thermal reliability in power systems, such as multi-chip power modules (MCPMs), through layout synthesis and simultaneous optimization of heat dissipation and electrical performance.
Peng is currently an Assistant Professor in the Computer Science and Computer Engineering Department at the University of Arkansas, Fayetteville, and is affiliated with the NSF-sponsored Engineering Research Center for Power Optimization of Electro-Thermal Systems. His research interests extend to high band-gap power electronics, high-efficiency digital designs, and memory systems. He has received funding from the National Science Foundation (NSF) for a CAREER award totaling $500,000, supporting his work on chiplet-package co-optimizations for 2.5D heterogeneous Systems-on-Chips (SoCs).
With a h-index of 15 and over 800 citations across more than 65 publications, Peng has collaborated with researchers including Imam Al Razi, Quang Trung Le, Tristan M. Evans, and MD Arafat Kabir at the University of Arkansas. He maintains an active laboratory website to showcase his group's work.
Metrics
- h-index: 15
- Publications: 63
- Citations: 806
Positions
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Junior Chair Professor 2025–presentSoutheast University Integrated Circuits ORCID
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Junior Chair Professor publications 2017–2025University of Arkansas at Fayetteville ORCID
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Assistant Professor 2023–2025University of Arkansas Electrical Engineering and Computer Science ORCID
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Summer Intern 2016Mentor Graphics Corp ORCID
Selected Publications
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PowerSynth 2: Automated Power Electronics Physical Design Synthesis With Custom and Heterogeneous Components (2025)
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Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System (2025)
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Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth (2023)
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VLSI-Inspired Design Automation for Scalable Power Electronics Layout Optimization (2023)
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A Comparative Study on Optimization Algorithms in PowerSynth 2 (2023)
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Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules (2023)
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Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules (2023)
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PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules (2022)
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Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth (2022)
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Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization (2022)
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Design Challenges of Intrachiplet and Interchiplet Interconnection (2022)
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Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses (2022)
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Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation (2021)
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Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method (2021)
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A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization (2021)
Federal Grants 1 $500,000 total
NSF
PI
Jun 2021 - May 2026
CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs
Collaboration Network
Top Collaborators
H. Alan Mantooth
University of Arkansas at Fayetteville
21 shared publications
In database
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization
Showing 5 of 21 shared publications
Imam Al Razi
Intel (United States)
17 shared publications
In database
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Physical Design Automation for High-Density 3D Power Module Layout Synthesis and Optimization
Showing 5 of 17 shared publications
Quang Trung Le
University of Arkansas at Fayetteville
15 shared publications
In database
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
Showing 5 of 15 shared publications
Tristan M. Evans
University of Arkansas at Fayetteville
13 shared publications
In database
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
Showing 5 of 13 shared publications
Shilpi Mukherjee
University of Arkansas at Fayetteville
8 shared publications
In database
- PowerSynth: A Power Module Layout Generation Tool
- PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules
- Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)
Showing 5 of 8 shared publications
Dusan Petranovic
Siemens (Hungary) (HU)
7 shared publications
- Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design
- Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs
- Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs
- Chip/package co-analysis and inductance extraction for fan-out wafer-level-packaging
- Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
Showing 5 of 7 shared publications
David Huitink
University of Arkansas at Fayetteville
6 shared publications
In database
- Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth
- PowerSynth-Guided Reliability Optimization of Multi-Chip Power Module
- Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- System-Level Thermal Management and Reliability of Automotive Electronics: Goals and Opportunities in the Next Generation of Electric and Hybrid Electric Vehicles
Showing 5 of 6 shared publications
Sung Kyu Lim
Georgia Institute of Technology (US)
5 shared publications
- Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Process
- Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs
- Interdie Coupling Extraction and Physical Design Optimization for Face-to-Face 3-D ICs
- Chip/package co-analysis and inductance extraction for fan-out wafer-level-packaging
- Die-to-package coupling extraction for fan-out wafer-level-packaging
Alan Mantooth
University of Arkansas at Fayetteville
4 shared publications
In database
- The Increasing Role of Design Automation in Power Electronics: Gathering What Is Needed
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
MD Arafat Kabir
University of Arkansas at Fayetteville
4 shared publications
In database
- Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools
- Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design
- Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization
- A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization
MD Arafat Kabir
Seva Mandir
4 shared publications
In database
- Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design
- Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
- Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study
- Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System
Tom Vrotsos
University of Arkansas at Fayetteville (US)
3 shared publications
- PowerSynth: A Power Module Layout Generation Tool
- Toward Partial Discharge Reduction by Corner Correction in Power Module Layouts
- Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs)
Whit Vinson
University of Arkansas at Fayetteville
3 shared publications
In database
- Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
David Agogo-Mawuli
University of Arkansas at Fayetteville
3 shared publications
In database
- Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
- Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules
Mehran Sanjabiasasi
University of Arkansas at Fayetteville
3 shared publications
In database
- Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth
- A Comparative Study on Optimization Algorithms in PowerSynth 2
- PowerSynth 2: Automated Power Electronics Physical Design Synthesis With Custom and Heterogeneous Components
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